Synopsys IC Compiler II W-2024.09-SP3 Linux 版发布，支持数亿级实例设计，适配FinFET先进工艺，提供并行优化与AI驱动技术，显著缩短设计周期并提升PPA。
原始标题：Synopsys IC Compiler II W-2024.09-SP3 Linux
- 高性能与高容量：支持处理数亿级实例的超大型设计，提供极快的规划、布局和布线收敛速度。
- 先进工艺支持：全面适配低节点 FinFET 及多重曝光等复杂物理约束，优化寄生参数和时序收敛。
- 并行优化架构：采用多线程和广泛的并行优化框架，实现多目标全局布局和功耗驱动优化。
- 机器学习与智能化：结合 AI 和机器学习驱动的优化技术，进一步缩短设计周期并提升 PPA 指标。
Synopsys, Inc. has released IC Compiler II W-2024.09-SP2 is a complete netlist-to-GDSII implementation system that includes early design exploration and prototyping, detailed design planning, block implementation, chip assembly and sign-off driven design closure.
IC Compiler II is the industry leading place and route solution that delivers best-in-class quality-of-results (QoR) for next generation designs across all market verticals and process technologies, while enabling unprecedented productivity. IC Compiler II includes innovative for flat and hierarchical design planning, early design exploration, congestion aware placement and optimization, clock tree synthesis, advanced node routing convergence, manufacturing compliance, and signoff closure.
IC Compiler II is specifically architected to address aggressive performance, power, area (PPA), and time-to-market pressures of leading edge designs. Key technologies include a pervasively parallel optimization framework, multi-objective global placement, routing driven placement optimization, full flow Arc based concurrent clock and data optimization, total power optimization, multi-pattern and FinFET aware flow and machine learning (ML) driven optimization for fast and predictive design closure. Advanced Fusion technologies offer signoff IR drop driven optimization, PrimeTime delay calculation within IC Compiler II, exhaustive path based analysis (PBA) and signoff ECO within place and route for unmatched QoR and design convergence.
Jiangtao Meng, Sr. R&D Manager at Synopsys, discusses how IC Compiler II and Fusion Compiler enable intelligent planning and implementation of complex interconnects through innovative Topological Interconnect Planning (TIP) technology to accelerate project schedules while achieving the highest performance designs.
Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia.
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