Fusion Compiler vX-2025.06：AI驱动的芯片PPA极致优化
新思科技Fusion Compiler vX-2025.06发布，基于统一数据模型与AI技术，实现RTL到GDSII的签核级设计，提升PPA达20%，缩短设计周期2倍，应对先进工艺挑战。
- 统一的数据模型 (Unified Data Model): 整个流程共享单一数据模型，消除了不同工具间的数据转换，从而将设计流程从传统的“迭代式”转变为“高收敛度”。
- 黄金签核分析骨干 (Signoff-driven): 直接集成了 Synopsys 的黄金签核工具引擎（如 PrimeTime、StarRC），在综合和布局阶段就能实现准确的时序、功耗和压降（IR Drop）分析。
- 极致的 PPA 优化: 通过更准确的物理信息和分析能力，Fusion Compiler 能够提供更高频率、更低功耗、更小面积的芯片设计，特别是在先进工艺下表现优异。
- 智能化功能 (AI-driven): 结合了机器学习（ML）技术，用于优化布局、提升密度和加快收敛速度。
- 高可扩展性: 支持超大规模芯片设计，有效应对前沿工艺带来的挑战。
Synopsys, Inc. has released Fusion Compiler vX-2025.06 is uniquely architected to enable design teams to achieve the optimal levels of power, performance, and area (PPA) in the most convergent manner to ensure the fastest and most predictable TTR.
Synopsys Fusion Compiler is the next generation RTL-to-GDSII implementation system architected to address the complexities of advanced process node design and deliver up to 20% improved quality-of-results (QoR) while reducing time-to-results (TTR) by 2X. Fusion Compiler is built on a compact, single data model that allows seamless sharing of Fusion Technology across the RTL-to-GDSII flow to enable hyper-convergent design closure.
The first monolithic RTL-to-GDSII, synthesis and place and route solution, enabling highly-convergent and predictable digital implementation.
Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia.
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