Synopsys发布CoreTools vY-2026.03 Linux版，含coreBuilder、coreAssembler、coreConsultant三大工具，支持IP-XACT标准封装、子系统组装及DesignWare IP配置生成。
原始标题：Synopsys CoreTools vY-2026.03 Linux
coreBuilder（IP 封装）：
- 独立于语言的 IP 封装工具，用于捕获设计意图、配置菜单和多抽象模型视图。
- 协助第三方或内部自定义 IP 转换并生成完全符合 IP-XACT 标准的视图和核心数据库（coreKit）。
coreAssembler（子系统组装与集成）：
- 提供图形化（GUI）和脚本（Tcl/命令行）环境，用于快速构建复杂的 IP 子系统（如 AMBA 架构的总线、外设互联等）。
- 自动生成互联逻辑、配置 RTL、创建测试平台（Testbench），并能自动导出子系统的标准 IP-XACT XML 描述。
coreConsultant（单核配置与实现）：
- 面向特定 IP 实例的配置引导工具，指导工程师完成无错的参数设置、仿真验证与综合。
- 在使用 Synopsys 官方提供的 DesignWare IP（如 PCIe、USB、DDR、各类基础外设）时，通常需要通过此工具进行代码生成。
Synopsys Inc., a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs, has released coreTools vY-2026.03 is a set of intellectual property (IP) packaging and integration tools for use in a knowledge-based design and verification flow.
The coreTool family includes:
coreBuilder – a robust packaging tool that allows designers to capture the knowledge and design intent of the IP and provide graphical or command based configuration menus for the IP. It supports the packaging of all the different model views of the IP needed engineering teams. This reduces IP support costs, improves quality and IP packaged with coreBuilder is fully compliant with the IP-XACT specification.
coreAssembler – an open IP assembly tool that automatically generates the interconnect and configured RTL, as well as documenting the block and system configuration details and design testbench. When combined with coreBuilder, entire subsystems can be packaged as coreKits enabling the easy creation configurable market targeted platforms. In addition to assembly and configuration designers are able to generate a starting testbench configured for the design so they can begin to validate there design. coreAssembler also will generate the IP-XACT XML for the design.
coreConsultant – the utility package for configuring, implementing and validating individual IP blocks packaged with coreBuilder. coreConsultant will also generate the IP-XACT XML for the IP block.
The Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools for use in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gains when using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the risk configuration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction in SoC or platform design time and achieve the highest QoR in the implementation of the design.
Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia.
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