本课程深入讲解数字IC与FPGA设计的常用硬件架构，包括SRAM、握手接口、同步FIFO、流水线、仲裁器、跨时钟域及异步FIFO等，助你迈向复杂IP设计。适合具备数字基础与Verilog知识的学员。
原始标题：Digital IC/FPGA Design P3:Common Used Hardware Architectures
Published 12/2024
Created by SKY SiliconThink
MP4 | Video: h264, 1280×720 | Audio: AAC, 44.1 KHz, 2 Ch
Level: All | Genre: eLearning | Language: English | Duration: 6 Lectures ( 2h 39m ) | Size: 1.1 GB
a big step towards complex IP design
What you’ll learn
Behavior of SRAM and usage suggestions
Handshake interface and synchronous FIFO
Pipeline to maximal clock frequency
Arbiter
Cross clock domain (CDC) and asynchronous FIFO
Ping-Pong
Pipeline with control (feedback)
Pipeline with hazard and forward path
Slide window
Requirements
Basic knowledge of digital fundamental
Basic C or C++ programing language
Basic Verilog Language
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